1. Field of the Invention
The present invention relates to a memory device and fabricating method thereof. More particularly, the present invention relates to a dynamic random access memory cell and fabricating method thereof.
2. Description of the Related Art
With each new generation of microprocessor functionally more powerful, the type of software programs that can be operated on is getting bigger and bigger. As a result, memory with an ever-increasing storage capacity and a faster access speed is demanded. Due to the increasing importance of memory storage capacity and operation speed, innovative technique for fabricating memory devices is always a major research target in the semiconductor industry.
In general, memory types can be categorized according to the storage state into volatile memory and non-volatile memory. Dynamic random access memory (DRAM) is a type of volatile memory constructed from an array of memory cells. Each memory cell comprises an active device and a capacitor. Furthermore, each memory cell is electrically connected to a word line (WL) and a bit line (BL).
According to the type of capacitor used in each memory cell, dynamic random access memory can be further sub-divided into a stack capacitor DRAM and a deep trench capacitor DRAM. Because the deep trench capacitor of a deep trench capacitor DRAM is formed deep within the substrate, planarization is less of a problem compared with a stack capacitor DRAM. Hence, deep trench capacitor DRAM is particularly suitable for fabricating smaller memory devices. However, more and more problems are still encountered in the process of fabricating the deep trench capacitor DRAM as the size of each device is reduced.
FIGS. 1A through 1D are schematic cross-sectional views showing the steps for fabricating a portion of a conventional DRAM with a deep trench capacitor. As shown in FIG. 1A, a substrate 100 is provided, and then a patterned pad layer 102 and a mask layer 104 are sequentially formed over the substrate 100. Thereafter, using the patterned pad layer 102 and the mask layer 104 as an etching mask, a deep trench 106 is formed in the substrate 100. A lower electrode 108 is formed in the substrate 100 at the bottom portion of the deep trench 106. After that, a capacitor dielectric layer 110 and a polysilicon layer 112 are sequentially formed over the bottom portion of the deep trench 106. A collar oxide layer 114 is formed over the mask layer 104 and on the exposed interior surface of the deep trench 106 where does the polysilicon layer 112 not cover.
As shown in FIG. 1B, an anisotropic etching process is carried out to remove the collar oxide layer 114 at the top portion of the mask layer 104 and the polysilicon layer 112. The remaining collar oxide layer forms a collar oxide layer 114a on the sidewall of the deep trench 106. Thereafter, polysilicon is deposited into the deep trench 106 to form a polysilicon layer 116.
As shown in FIG. 1C, a portion of the polysilicon layer 116 outside the deep trench 106 and a portion of the polysilicon layer 116 inside the trench 106 are removed to form a polysilicon layer 116a. Thereafter, the exposed collar oxide layer 114a is removed to form a collar oxide layer 114b. Polysilicon is deposited into the deep trench 106 to form a polysilicon layer 118. The polysilicon layers 112, 116a and 118 are electrically connected together to form the upper electrode of the deep trench capacitor.
As shown in FIG. 1D, a thermal process is carried out to trigger the out-diffusion of dopants inside the polysilicon layer 118 into the substrate 100. Hence, a buried strap (BS) 120 is formed in the substrate 100 around the polysilicon layer 118. The buried strap 120 has a buried strap window 122. Thereafter, a shallow trench isolation (STI) process is carried out to form a STI structure 124 in the substrate 100 adjacent to the polysilicon layer 118 and form a polysilicon layer 118a. The STI structure 124 also defines an active region (not shown). After that, the pad layer 102 and the mask layer 104 are removed. Then, a gate structure 126 is formed on the active region of the substrate 100 and another gate structure 128 is formed on the STI structure 124. A source region 130a and a drain region 130b are formed in the substrate 100 on each side of the gate structure 126. The drain region 130b is electrically connected to the upper electrode of the deep trench capacitor through the buried strap 120.
However, the size of the buried strap window 122 formed by the aforementioned DRAM fabrication process influences the performance of the DRAM device. For example, if the buried strap window is too large, leakage current will be a significant problem for the device. On the other hand, if the buried strap window is too small, the resistance between the buried strap and the upper electrode may be too high leading to a significant drop in the performance of the device. Therefore, the size of the buried strap window has become one of the critical factors affecting the performance of DRAM devices.